1. Field of the Invention
The present invention relates to a semiconductor memory including flip flop type memory cells and specifically to the technique of controlling the low-data holding power supply, high-data holding power supply, bit-line precharging power supply of the memory cells.
2. Description of the Prior Art
In recent years, along with the advancement of process miniaturization, the reduction in area of semiconductor integrated circuits and the decrease in supply voltage have been achieved on an accelerated basis. A disadvantage of these achievements is, for example, in the case of a semiconductor memory including flip flop type memory cells, such as a static random access memory (SRAM), a considerable difficulty in achieving stable memory cell characteristics due to variations in characteristics among transistors constituting memory cells or the decrease in supply voltage. As a result of this disadvantage, the yield of such a semiconductor memory undesirably decreases due to static noise margin (SNM) or deterioration in write characteristics.
FIG. 15 is a 1-port SRAM memory cell of a general flip flop type, which is formed by CMOS transistors. In FIG. 15, the memory cell includes drive transistors QN1 and QN2, access transistors QN3 and QN4, and load transistors QP1 and QP2. Reference numeral WL denotes a word line. Reference numerals BL and BLX denote bit lines. Reference numeral VDD denotes a power supply.
The load transistor QP1 and the drive transistor QN1 constitute an inverter. The load transistor QP2 and the drive transistor QN2 constitute another inverter. The input and output terminals of these inverters are cross-coupled to form a flip flop. Herein, the output terminal of each inverter is referred to as “data memory node”. The power supply which is coupled to the sources of the load transistors QP1 and QP2 is referred to as “high-data holding power supply”.
The gate terminals of the access transistors QN3 and QN4 are connected to the same word line WL. The drain terminal of the access transistor QN3 is connected to the bit line BL. The drain terminal of the access transistor QN4 is connected to the bit line BLX. The source terminals of the access transistors QN3 and QN4 are connected to the output terminals of the aforementioned inverters.
Writing of data in the SRAM memory cell of FIG. 15 is achieved by pulling the potential of one of the bit lines BL and BLX, which have been precharged to H (high) level, from H level to L (low) level while the word line WL is at H level (active state).
The memory cell characteristics of SRAM generally include the write level and the static noise margin.
The write level represents the write voltage to a memory cell. The operation of writing data in an SRAM memory cell is achieved by inverting the state of a flip flop included in the memory cell (provided, however, that when data identical to the write data is stored in the memory cell in advance, the state of the flip flop is not inverted). Herein, the critical potential of the bit line at which the state of the flip flop of the memory cell is invertible is referred to as “write level”.
For example, when the write level is low, the margin for an erroneous writing due to bit line noise (static noise margin) becomes large in a write operation. However, the time required for the write operation becomes long because the flip flop cannot be inverted before the potential of the bit line reaches a sufficiently low level. On the other hand, when the write level is high, the margin for an erroneous writing (static noise margin) becomes small, although the time required for the write operation becomes short.
The write level being low means that the state of the flip flop of the memory cell unreadily inverts in the read operation due to bit line noise, or the like, i.e., that the static noise margin becomes large. The write level being high means that the state of the flip flop of the memory cell readily inverts in the read operation, i.e., that the static noise margin becomes small.
As described above, the write level and the static noise margin have conflicting characteristics with each other such that one of these characteristics cannot be satisfied without decreasing the other characteristic margin.
In view of such circumstances, there has been a proposal that at least one of these characteristics is ameliorated. For example, a semiconductor memory constructed with a view to improving only the write level has been known wherein the voltage of the high-data holding power supply of a memory cell is controlled so as to be low in a write operation, whereby the write level is ameliorated (see, for example, Japanese Laid-Open Patent Publication No. 55-64686).
On the other hand, the SRAM can be constructed in the form of a so-called 2-port SRAM wherein both write and read operations can be performed in one access. FIG. 16 shows a structure of a commonly-employed 2-port SRAM. This 2-port SRAM has a flip flop similar to that of the SRAM of FIG. 15 and further includes a pair of access transistors QN10 and QN11 which are connected to a data memory node of the flip flop, a word line WL2 for controlling the access transistors QN10 and QN11, and a pair of bit lines BL2 and BL2X (see, for example, 2004 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 508-510). The flip flop of the 2-port SRAM itself has the same structure as that of the 1-port SRAM, and therefore, the 2-port SRAM has the same characteristics for read and write operations as the 1-port SRAM.
However, in a semiconductor memory in which the voltage of the high-data holding power supply of the memory cell is controlled as described above, the writing level is ameliorated but, when the high-data holding power supply of the memory cell is controlled to have a low voltage, the static noise margin is deteriorated.
In a normal case, it is necessary for improving the static nose margin to set the potential of an activated word line lower than the high-data holding supply potential of the memory cell.
However, when the potential of the word line is decreased, the write level deteriorates on the other hand. Thus, even if the high-data holding supply voltage of the memory cell is decreased in a write operation such that the write level is ameliorated, the effect of such an arrangement is marred by a decrease in potential of the word line.
A normally-employed semiconductor memory has a matrix structure consisting of selected columns, unselected columns, selected word lines, and unselected word lines. Therefore, the word line potential cannot be selectively high or low only at a crossing point of a selected column and a selected word line.
However, when a word line is selected for a write operation, the static noise margin undesirably deteriorates (writing occurs) in memory cells of unselected columns present on the same selected word line even though it is not intended.
In the case of a 2-port SRAM, the following problems arise in addition to the above-described disadvantages of the 1-port SRAM.
In the 1-port SRAM, normally, either of read and write operations is performed in one access from one input-output circuit connected to a pair of bit lines to one memory cell. In the 2-port SRAM, on the other hand, a read or write operation can be simultaneously carried out on two memory cells through different input-output circuits connected to two pairs of bit lines. That is, there are two selected word lines and two selected column lines at the maximum for simultaneously accessing two memory cells. This enables the following operational procedures: different operations, i.e., read and write operations, simultaneously occur on two memory cells selected by different selected column lines on the same selected word line; or different operations, i.e., read and write operations, simultaneously occur on two memory cells selected by different selected word lines on the same selected column line.
Therefore, the conventional technique of ameliorating only the read margin (static noise margin) or write margin (write level) by the control of the word line level in the word line direction or the control of the high-data holding power supply in the column direction cannot comply with such a semiconductor memory as a 2-port SRAM wherein write and read operations for memory cells on the same selected line are simultaneously carried out.